%0 Journal Article
%T Online Testable Decoder using Reversible Logic
%A Hemalatha. K. N. Manjula B. B. Girija. S
%J International Journal of Electronics Communication and Computer Engineering
%D 2012
%I IJECCE
%X The project proposes to design and test 2 to 4 reversible Decoder circuit with arbitrary number of gates to an online testable reversible one and is independent of the type of reversible gate used. The constructed circuit can detect any single bit errors and to convert a decoder circuit that is designed by reversible gates to an online testable reversible decoder circuit. Conventional digital circuits dissipate a significant amount of energy because bits of information are erased during the logic operations. Thus if logic gates are designed such that the information bits are not destroyed, the power consumption can be reduced. The information bits are not lost in case of a reversible computation. Reversible logic can be used to implement any Boolean logic function.
%K Reversible logic
%K Feyman gate
%K NOT Gate
%K Fredkin Gate
%K Deduced reversible gate DRG
%K Testable reversible gate TRC
%K Test Cell TC
%U http://www.ijecce.org/administrator/components/com_jresearch/files/publications/142PA.pdf