%0 Journal Article
%T Design, Implementation and Performance Analysis of Low Power, Low Energy Adder Using Adibatic Logic in 45nm CMOS Sub-micron Technology
%A Jitendra R. Patel
%A Prof. Sandip Nemade
%A Prof. Vikas Gupta
%J International Journal of Engineering Innovations and Research
%D 2013
%I IJEIR
%X In this paper I had implemented the different two types of 1-bit adder using adiabatic logic and conventional CMOS logic in 45nm technology with LT spice. As we know Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. Apart from the basic addition adders also used in performing useful operations such as subtraction, multiplication, division, address calculation, etc. we have compared the complementary pass transistor (CPL) logic and 2 phase clocked adiabatic static CMOS logic (2PASCL) 1-bit adder for power dissipation as well as energy consumption, result suggest adiabatic method has low power and low energy consumption compared to complementary pass transistor logic.
%K Adibatic Logic
%K CPL
%K 2PASCL
%K DSP
%K CMOS
%K low power
%U http://journals.indexcopernicus.com/fulltxt.php?ICID=1050555