%0 Journal Article
%T High speed 22nm Metal Gate Strained Si CMOS NAND gate
%A Shobha Sharma
%A Ashwani Kumar
%A Nupur Prakash
%A B.V.R. Reddy
%J International Journal of Innovative Technology and Exploring Engineering
%D 2013
%I IJITEE
%X ¡ªThe paper shows the research on the NAND gate at22 nm technology node with Hik metal gate technology withforward body biasing. The use of forward static body biasingresults in high speed but at the cost of increased power dissipationand deterioration in the output voltage levels, if forward bodybiasing is beyond a certain limit of supply voltage. The circuitshown may be used for high speed application where powerconsumption and dissipation is not the priority. The circuit shownmay be further modified to result in much further increase inspeed but with degradation in the maximum and minimum levelsof output voltage. For the future work, the voltage levels can berestored at the cost of increased area if Forward body biasing is onthe higher value and hence poor output levels of high and lowvalue. The circuit simulations are done with Arizona stateuniversity predictive technology models of high performancecategory at 22nm node with HiK Metal gate strained SiliconTechnology. The new NAND gate at with forward body biasing inthe PMOS & NMOS Transistor shows and highlights theimportance of forward body biasing resulting in higher speed atthe cost of slight increase in power with zero increase of areacompared to standard CMOS NAND gate and no deterioration ofoutput voltage levels.
%K 22nm
%K body biasing
%K high speed NAND
%K Hik Metal gate
%K strained Silicon
%U http://www.ijitee.org/attachments/File/v3i3/C1058083313.pdf