%0 Journal Article
%T Gate Stack Engineering and Thermal Treatment on Electrical and Interfacial Properties of Ti/Pt/HfO2/InAs pMOS Capacitors
%A Chung-Yen Chien
%A Jei-Wei Hsu
%A Pei-Chin Chiu
%A Jen-Inn Chyi
%A Pei-Wen Li
%J Active and Passive Electronic Components
%D 2012
%I Hindawi Publishing Corporation
%R 10.1155/2012/729328
%X Effects of gate stack engineering and thermal treatment on electrical and interfacial properties of Ti/Pt/HfO2/InAs metal insulator semiconductor (MIS) capacitors were systematically evaluated in terms of transmission electron microscopy, energy dispersive X-ray spectroscopy, current-voltage, and capacitance-voltage characterizations. A 10 nm thick Pt metal effectively suppresses the formation of interfacial oxide, TiO2, between the Ti gate and HfO2 gate dielectric layer, enhancing the gate modulation on the surface potential of InAs. An in situ HfO2 deposition onto the n-InAs channel with an interfacial layer (IL) of one-monolayer InP followed by a 300¡ãC post-metal-anneal produces a high-quality HfO2/InAs interface and thus unravels the annoying Fermi-level pinning, which is evidenced by the distinct capacitance dips in the high-/low-frequency C-V characteristics. The interface trap states could be further suppressed by replacing the InP IL by an As-rich InAs, which is substantiated by a gate leakage reduction and a steep voltage-dependent depletion capacitance. 1. Introduction Motivation to study low band-gap InAs and InSb channels for next-generation metal oxide semiconductor (MOS) transistors is strong in light of their superior carrier mobility [1] and established epitaxy techniques [2, 3] among other emerging technologies such as carbon nanotube and graphite. However, the progress of realizing high-performance InAs and InSb MOS transistors has been impeded by the stringent restraint on thermal budget as well as the lack of robust gate dielectrics and suitable surface treatments for unraveling annoying Fermi-level pinning [4] at the oxide/semiconductor interface. Recently encouraging experimental demonstrations of high- gate dielectrics (Gd2O3, Al2O3, and HfO2) on GaAs [5¨C7], InP [8], and InAs [9¨C11] channels using atomic-layer deposition (ALD) techniques have shed lights and attracted tremendous attentions on this venerable subject. In spite that various chemical and plasma surface treatments [12¨C14] have been proposed for annihilating surface states of III-V compound semiconductors, it still remains elusive how to produce a clean and well-passivated channel surface for subsequent high-quality gate dielectric growth. The most practical and promising approach for the surface preparation of III-V channels appears to be the in situ growth of gate dielectrics on channels. In this paper, the authors report the interfacial and electrical properties of Ti/Pt/HfO2/InAs pMOS capacitors, in which a high- gate dielectric, HfO2 was grown on an -InAs epitaxial
%U http://www.hindawi.com/journals/apec/2012/729328/