%0 Journal Article
%T Profiling on Superscalar Pipelining Architecture and Multi-Pipeline Scheduling Policies
%A Tarun Bhalla
%A Mohit Mittal
%J International Journal of Computer & Electronics Research
%D 2012
%I Eoryx Publications
%X In this paper, we present the process of pipelining using superscalar processor. A super-scalar processor is one that is capable of sustaining an instruction-execution rate of more than one instruction per clock cycle. Maintaining this execution rate is primarily a problem of scheduling processor resources (such as functional units) for high utilization. Multiple pipes are used for improving the performance of pipelining. A superscalar processor can be envisioned having multiple parallel pipelines, each of which is processing instructions simultaneously from a single instruction thread.
%K superscalar pipeline design
%K pipeline stalling
%K multipipeline scheduling i.e. in-order issue & in-order completion
%K in-order issue & out-order completion and out-order issue & out-order completion
%U http://ijcer.org/index.php/ojs/article/view/61