%0 Journal Article
%T Implementation of High-Performance Image Scaling Processor using VLSI
%A R.S. KARTHIC
%J International Journal of Computer Science and Mobile Computing
%D 2013
%I 
%X In this paper, a less complexity, less memoryrequirement, and high performance algorithm is proposed for VeryLarge Scale Integration implementation of an image scalingprocessor. The anticipated image scaling algorithm consists of aclamp filter, spatial filter and a bilinear interpolation. The spatialand clamp filters are added as pre-filters for reducing the aliasingartifacts resulted by the bilinear interpolation. A T-model andinversed T-model convolution kernels are proposed to reduce thecomplexity of the design. Combined filter is replaced by a dynamicestimation unit to minimize the hardware cost. This architecture istargeted to produce 320MHz with 6.08-K gate counts. Comparedwith Previous methodologies, this work shows better performancewith respect to cost and less complexity.
%K Clamp filter
%K Image zooming
%K Dynamic estimation unit
%K Bilinear
%K Spatial filter
%K VLSI
%U http://www.ijcsmc.com/docs/papers/April2013/V2I4201308.pdf