%0 Journal Article
%T A Novel Architecture for Super Speed Data Communication for USB 3.0 Device Using FPGA
%A Amit Kumar Amod
%A Ansuman DiptiSankar Das
%A Tapas Sahu
%A Sekhar Sahani
%J International Journal of Recent Technology and Engineering
%D 2013
%I IJRTE
%X The need for SuperSpeed data communication leads to the use of USB 3.0. USB 3.0 utilizes dual bus architecture which provides both SuperSpeed and non-SuperSpeed connectivity. This can be possible by mixing the advantage of parallel and serial data transfer. This paper provides a novel architecture for communication between USB 3.0 device and USB 3.0 host controller at a data rate of maximum up to 5.0 Gbps using Altera¡¯s Stratix IV FPGA. To maintain synchronization between GPIF II and PCIe hard IP, FIFO is used. PLL is used to provide clock signal at different frequencies.
%K FIFO
%K FPGA
%K GPIF
%K Hard IP
%K PLL
%K USB 3.0.
%U http://www.ijrte.org/attachments/File/v2i1/A0515032113.pdf