%0 Journal Article
%T FPGA Implementation of a 64-Bit RISC Processor Using VHDL
%A Imran Mohammad
%A Ramananjaneyulu K
%J International Journal of Reconfigurable and Embedded Systems (IJRES)
%D 2012
%I Institute of Advanced Engineering and Science (IAES)
%R 10.11591/ijres.v1i2.449
%X In this paper, the Field Programmable Gate Array (FPGA) based 64-bit RISC processor with built-in-self test (BIST) feature implemented using VHDL and was, in turn, verified on Xilinx ISE simulator. The VHDL code supports FPGA, System-On-Chip (SOC), and Spartan 3E kit. This paper also presents the architecture, data path and instruction set (IS) of the RISC processor. The 64-bit processors, on the other hand, can address enormous amounts of memory up to 16 Exabyte¡¯s. The proposed design can find its applications in high configured robotic work-stations such as, portable pong gaming kits, smart phones, ATMs.
%U http://iaesjournal.com/online/index.php/IJRES/article/view/449