%0 Journal Article
%T CMOS DESIGN AND LOW POWER FULL ADDER USING .12 MICRON TECHNOLOGY
%A Arun Gangwar
%A Rajesh Mehra
%J International Journal of Research in Computer Applications and Robotics
%D 2013
%I 
%X In this paper, we are presenting a 8T full adder using 1-bit consuming less power than a conventional adderusing 24T.The main objective is to design that 8T circuit with low power consumption and due to its reducedtransistor count, a very low power full adder is realized. The circuit is optimized at .12 micron CMOStechnology .The conventional is compared to 8T Full adder based on power consumption, speed and powerdelay intensive simulation runs on microwind technology shows now 8T adder has 60-70% power saving overconventional one.General Terms: 24T and 8T
%K Full adder
%K Microwind simulator
%K VLSI circuit and low power
%U http://ijrcar.in/Volume%201%20Issue%202/v1i215.pdf