%0 Journal Article
%T Design of a Parallel Sampling Encoder for Analog to Information (A2I) Converters: Theory, Architecture and CMOS Implementation
%A Thomas S. Murray
%A Philippe O. Pouliquen
%A Andreas G. Andreou
%J Electronics
%D 2013
%I MDPI AG
%R 10.3390/electronics2010057
%X We discuss the architecture and design of parallel sampling front ends for analog to information (A2I) converters. As a way of example, we detail the design of a custom 0.5 ¦Ìm CMOS implementation of a mixed signal parallel sampling encoder architecture. The system consists of configurable parallel analog processing channels, whose output is sampled by traditional analog-to-digital converters (ADCs). The analog front-end modulates the signal of interest with a high-speed digital chipping sequence and integrates the result prior to sampling at a low rate. An FPGA is employed to generate the chipping sequences and process the digitized samples.
%K analog to information converter
%K sub-Nyquist sampling
%K compressive sensing
%K parallel ADCs
%U http://www.mdpi.com/2079-9292/2/1/57