%0 Journal Article
%T Influence of Series Massive Resistance on Capacitance and Conductance Characteristics in Gate-Recessed Nanoscale SOI MOSFETs
%A Avraham Karsenty
%A Avraham Chelly
%J Active and Passive Electronic Components
%D 2013
%I Hindawi Publishing Corporation
%R 10.1155/2013/813518
%X Ultrathin body (UTB) and nanoscale body (NSB) SOI MOSFET devices, having a channel thickness ranging from 46£¿nm (UTB scale) down to 1.6£¿nm (NSB scale), were fabricated using a selective ¡°gate recessed¡± process on the same silicon wafer. The gate-to-channel capacitance and conductance complementary characteristics, measured for NSB devices, were found to be radically different from those measured for UTBS. Consistent and trends are observed by varying the frequency , the channel length , and the channel thickness ( ). In this paper, we show that these trends can be analytically modeled by a massive series resistance depending on the gate voltage and on the channel thickness. The effects of leakage conductance and interface trap density are also modeled. This modeling approach may be useful to analyze and/or simulate electrical behavior of nanodevices in which series resistance is of a great concern. 1. Introduction Planar Fully-Depleted Silicon-On-Insulator (FD-SOI) technology relies on a silicon wafer having an ultrathin layer of crystalline silicon smartly built over a Buried Oxide layer (commonly called BOX). Transistors built into this top silicon layer (which thickness ranges in the decananometer thickness) are called Ultrathin Body (UTB) devices. Such devices have unique and extremely attractive characteristics for coming technology nodes. Since performance needs are increased together with power consumption control, UTB/FD-SOI is also a key technology for addressing high speed and leakage control. In the past several years this technology has gained significant momentum in the mobile communications market space [1, 2]. FD-SOI devices were deeply analyzed across the literature, including the influence of the BOX/Si interface [3]. However, if characterization and modeling of gate-to-channel capacitance and conductance in FD-SOI devices were recently presented [4], the analyses were focused on devices with gate lengths down to 35£¿nm and channel thickness down to 8£¿nm. In parallel, characterization and parameter extraction methods [5, 6], including CV-based method [7], were developed to emphasize dependences between parameters. In this paper, we report the influence of the silicon channel thickness on the - characteristics of Nanoscale Body (NSB) SOI MOSFET devices having a channel thickness less than 5£¿nm and obtained by a selective gate recessed process [8]. We present a semiquantitative model allowing to justify the influence of the series resistance and to discriminate the influence of the surface states on the - characteristics. A preliminary
%U http://www.hindawi.com/journals/apec/2013/813518/