%0 Journal Article
%T A Novel Nanoscale FDSOI MOSFET with Block-Oxide
%A Jyi-Tsong Lin
%A Yi-Chuen Eng
%A Po-Hsieh Lin
%J Active and Passive Electronic Components
%D 2013
%I Hindawi Publishing Corporation
%R 10.1155/2013/627873
%X We demonstrate improved device performance by applying oxide sidewall spacer technology to a block-oxide-enclosed Si body to create a fully depleted silicon-on-insulator (FDSOI) nMOSFET, which overcomes the need for a uniform ultrathin silicon film. The presence of block-oxide along the sidewalls of the Si body significantly reduces the influence of drain bias over the channel. The proposed FDSOI structure therefore outperforms conventional FDSOI with regard to its drain-induced barrier lowering (DIBL), on/off current ratio, subthreshold swing, and threshold voltage rolloff. The new FDSOI structure is in fact shown to behave similarly to an ultrathin body (UTB) SOI but without the associated disadvantages and technological challenges of the ultrathin film, because a thick Si body allows for reduced sensitivity to self-heating, thereby improving thermal stability. 1. Introduction Semiconductor science, triggered by the impetus of a growing market for faster, more reliable, and less costly chips, has been undergoing a rapid technological development [1]. Many of these new technologies, however, suffer from undesirable side effects. For example, as the gate length of CMOS¡ªthe bulk complementary metal-oxide semiconductor¡ªis decreased, short-channel effects (SCEs), such as drain-induced barrier lowering (DIBL) and threshold voltage ( ) rolloff, become a significant problem because S/D encroachment begins to limit the gate¡¯s ability to control the channel. Also, due to the existence of the PN junction between the Si substrate and the S/D regions, a large junction leakage current prevents the use of scaled-down transistors in low standby power (LSTP) applications. Moreover, the parasitic capacitance of the transistor may strongly affect the characteristics of CMOS devices [2¨C4]. Therefore, the use of planar technology for ultralarge-scale integrated (ULSI) circuits becomes more challenging. Recently, silicon-on-insulator (SOI) technology has demonstrated promise for nano-CMOS scaling. Compared to its bulk Si counterparts, SOI offers reduced capacitance and lower OFF-state leakage current ( ), mainly due to the presence of a buried oxide (BOX) layer under the Si active layer [5]. This can be attributed to the fact that the BOX can be seen as a ¡°blocking layer¡± to reduce the drain electric field. Also, because the active region is fully isolated, it avoids the latch-up problem of classical CMOS devices. The benefits of SOI technology, however, are not without associated problems. A partially depleted (PD) SOI transistor cannot achieve an improved performance in
%U http://www.hindawi.com/journals/apec/2013/627873/