%0 Journal Article
%T Network Partitioning Domain Knowledge Multiobjective Application Mapping for Large-Scale Network-on-Chip
%A Yin Zhen Tei
%A Yuan Wen Hau
%A N. Shaikh-Husin
%A M. N. Marsono
%J Applied Computational Intelligence and Soft Computing
%D 2014
%I Hindawi Publishing Corporation
%R 10.1155/2014/867612
%X This paper proposes a multiobjective application mapping technique targeted for large-scale network-on-chip (NoC). As the number of intellectual property (IP) cores in multiprocessor system-on-chip (MPSoC) increases, NoC application mapping to find optimum core-to-topology mapping becomes more challenging. Besides, the conflicting cost and performance trade-off makes multiobjective application mapping techniques even more complex. This paper proposes an application mapping technique that incorporates domain knowledge into genetic algorithm (GA). The initial population of GA is initialized with network partitioning (NP) while the crossover operator is guided with knowledge on communication demands. NP reduces the large-scale application mapping complexity and provides GA with a potential mapping search space. The proposed genetic operator is compared with state-of-the-art genetic operators in terms of solution quality. In this work, multiobjective optimization of energy and thermal-balance is considered. Through simulation, knowledge-based initial mapping shows significant improvement in Pareto front compared to random initial mapping that is widely used. The proposed knowledge-based crossover also shows better Pareto front compared to state-of-the-art knowledge-based crossover. 1. Introduction The advancement in submicron technology allows more intellectual property (IP) cores to be integrated into a single chip which increases the system complexity. Multiprocessor system-on-chip (MPSoC) size will increase from several cores to hundreds of cores per chip in the future. Current on-chip communication architectures that utilize bus sharing or hierarchical bus architecture will become the performance bottleneck with the increasing number of cores. Implementation of large MPSoC needs more flexible communication resources. Network-on-chip (NoC) has emerged as a new communication architecture that provides modularity and flexibility for MPSoC. NoC architectures are based on traditional interconnection network concepts [1]. Each IP core is connected to one of the routers on the NoC network and messages are forwarded through routers to destination cores. However, a handful of NoC-based system design problems are still under research. The problems have been identified and categorized in [2]. A major challenge in NoC design is the placement of IP cores to the associated routers on the network. Application mapping determines the placement of IP cores to routers in the network such that the performance or cost metrics of interest are optimized [2]. In this paper, it
%U http://www.hindawi.com/journals/acisc/2014/867612/