%0 Journal Article
%T A 50.5 ns Wake-Up-Latency 11.2 pJ/Inst Asynchronous Wake-Up Controller in FDSOI 28 nm
%A Adam Makosiej
%A Alexandre Valentian
%A David Coriat
%A Edith Beign¨¦
%A Eric Guthmuller
%A Florent Berthier
%A Fr¨¦d¨¦ric Heitzmann
%A Ivan Miro-Panades
%A Jean-Fr¨¦d¨¦ric Christmann
%A Olivier Debicki
%A Pascal Vivet
%A S¨¦bastien Thuries
%A Yvain Thonnart
%J -
%D 2019
%R https://doi.org/10.3390/jlpea9010008
%X Abstract Due to low activity in Internet of Things (IoT) applications, systems tend to leverage low power modes in order to reduce their power consumption. Normally-off computing thus arose, consisting in having turned off most part of a system¡¯s power supply, while dynamically turning on components as the application needs it. As wake up sources may be diverse, simple controllers are integrated to handle smart wake up schemes. Therefore, to prevent overconsumption while transitioning to running mode, fast wake up sequences are required. An asynchronous 16-bit Reduced Instruction Set Computer (RISC) Wake-up Controller (WuC) is proposed demonstrating 50.5 [email protected] Million Instructions Per Second (MIPS)@0.6 V wake-up latency, drastically reducing the overall wake-up energy of IoT systems. A clockless implementation of the controller saves the booting time and the power consumption of a clock generator, while providing high robustness to environmental variations such as supply voltage level. The WuC is also able to run simple tasks with a reduced Instruction Set Architecture (ISA) and achieves as low as 11.2 pJ/inst @0.5 V in Fully Depleted Silicon On Insulator (FDSOI) 28 nm. View Full-Tex
%K wake-up controller
%K IoT
%K QDI asynchronous logic
%K normally-off computing
%K big/little architecture
%U https://www.mdpi.com/2079-9268/9/1/8