%0 Journal Article
%T Physical Parameter Variation Analysis on  the Performance Characteristics of Nano DG-MOSFETs
%A Yashu Swami
%A Sanjeev Rai
%J Circuits and Systems
%P 39-53
%@ 2153-1293
%D 2021
%I Scientific Research Publishing
%R 10.4236/cs.2021.124004
%X DG-MOSFETs are the most widely explored device
architectures for na</span></span><span style=\"font-family:Verdana;\"><span style=\"font-family:Verdana;\"><span style=\"font-family:Verdana;\">no-scale CMOS circuit design in
sub-50 nm due to the improved subthre</span></span></span><span><span><span style=\"font-family:&quot;\"><span style=\"font-family:Verdana;\">shold slope and the reduced leakage power compared to bulk MOSFETs. In thin-film
(</span><i><span style=\"font-family:Verdana;\">t</span><sub><span style=\"font-family:Verdana;\">si</span></sub></i><span style=\"font-family:Verdana;\"> &lt; 10 nm) DG-MOS
structures, charge carriers are affected</span></span></span></span><span style=\"font-family:Verdana;\"><span style=\"font-family:Verdana;\"><span style=\"font-family:Verdana;\"> by</span></span></span><span><span><span style=\"font-family:&quot;\"> <i><span style=\"font-family:Verdana;\">t</span><sub><span style=\"font-family:Verdana;\">si</span></sub></i><span style=\"font-family:Verdana;\">-</span></span></span></span><span><span><span style=\"font-family:&quot;\"> </span></span></span><span style=\"font-family:Verdana;\"><span style=\"font-family:Verdana;\"><span style=\"font-family:Verdana;\">induced
quantum confinement along with the confinement caused by </span></span></span><span style=\"font-family:Verdana;\"><span style=\"font-family:Verdana;\"><span style=\"font-family:Verdana;\">a </span></span></span><span><span><span style=\"font-family:&quot;\"><span style=\"font-family:Verdana;\">very
high electric field at the interface. Therefore, quantum confinement effects on
the device characteristics are also quite important and it needs to be incorpo</span><span style=\"font-family:Verdana;\">rated along with short channel effects for
nano-scale circuit design. In this</span> </span></span></span><span style=\"font-family:Verdana;\"><span style=\"font-family:Verdana;\"><span style=\"font-family:Verdana;\">paper</span></span></span><span style=\"font-family:Verdana;\"><span style=\"font-family:Verdana;\"><span style=\"font-family:Verdana;\">, we analyze</span></span></span><span style=\"font-family:Verdana;\"><span style=\"font-family:Verdana;\"><span style=\"font-family:Verdana;\">d</span></span></span><span style=\"font-family:Verdana;\"><span style=\"font-family:Verdana;\"><span style=\"font-family:Verdana;\"> a DG-MOSFET structure at </span></span></span><span style=\"font-family:Verdana;\"><span style=\"font-family:Verdana;\"><span style=\"font-family:Verdana;\">the </span></span></span><span style=\"font-family:Verdana;\"><span
%K Nano DG-MOSFET
%K Quantum Confinement Effects
%K Thin Film Structures
%K Short Channel Effects
%K Performance Characteristics
%U http://www.scirp.org/journal/PaperInformation.aspx?PaperID=114020