%0 Journal Article
%T New High-Performance Full Adders Using an Alternative Logic Structure
%A Linares Aranda
%A M¨®nico
%A Aguirre Hern¨˘ndez
%A Mariano
%J Computaci¨®n y Sistemas
%D 2011
%I Instituto Polit¨¦cnico Nacional
%X this paper presents two new high-speed low-power 1-bit full-adder cells using an alternative logic structure, and the logic styles dpl and sr-cpl. the adders were designed using electrical parameters of a 0.35¦Ěm complementary metal-oxide-semiconductor (cmos) process, and were compared with various adders published previously, with regards of power-delay product. to validate the performance simulation results of one of the proposed adders, an 8-bits pipelined multiplier was fabricated using a 0.35¦Ěm cmos technology, and it showed to provide superior performance.
%K full-adder
%K low-power
%K multiplier
%K pipeline.
%U http://www.scielo.org.mx/scielo.php?script=sci_abstract&pid=S1405-55462011000100002&lng=en&nrm=iso&tlng=en