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OALib Journal期刊
ISSN: 2333-9721
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International Journal of Reconfigurable Computing
ISSN Print: 1687-7195
ISSN Online:
主页:
http://www.hindawi.com/journals/ijrc/
分享:
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Efficient FPGA Hardware Reuse in a Multiplierless Decimation Chain
Guillermo A. Jaquenod
,
Javier Valls
,
Javier Siman
IP-Enabled C/C++ Based High Level Synthesis: A Step towards Better Designer Productivity and Design Performance
Sharad Sinha
,
Thambipillai Srikanthan
An Asynchronous FPGA Block with Its Tech-Mapping Algorithm Dedicated to Security Applications
Taha Beyrouthy
,
Laurent Fesquet
Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units
Jo?o Bispo
,
Nuno Paulino
,
Jo?o M. P. Cardoso
,
Jo?o Canas Ferreira
Development of a SoC for Digital Television Set-Top Box: Architecture and System Integration Issues
André Borin Soares
,
Alexsandro Cristóvão Bonatto
,
Altamiro Amadeu Susin
Runtime Scheduling, Allocation, and Execution of Real-Time Hardware Tasks onto Xilinx FPGAs Subject to Fault Occurrence
Xabier Iturbe
,
Khaled Benkrid
,
Chuan Hong
,
Ali Ebrahim
Selected Papers from the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011)
René Cumplido
,
Peter Athanas
,
Jürgen Becker
A Heuristic Scheduler for Port-Constrained Floating-Point Pipelines
Zheming Jin
,
Jason D. Bakos
Fully Pipelined Implementation of Tree-Search Algorithms for Vector Precoding
Maitane Barrenechea
,
Mikel Mendicute
,
Egoitz Arruti
Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs
Malte Baesler
,
Sven-Ole Voigt
Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs
Malte Baesler
,
Sven-Ole Voigt
A Heuristic Scheduler for Port-Constrained Floating-Point Pipelines
Zheming Jin
,
Jason D. Bakos
Fully Pipelined Implementation of Tree-Search Algorithms for Vector Precoding
Maitane Barrenechea
,
Mikel Mendicute
,
Egoitz Arruti
Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units
Jo?o Bispo
,
Nuno Paulino
,
Jo?o M. P. Cardoso
,
Jo?o Canas Ferreira
An Asynchronous FPGA Block with Its Tech-Mapping Algorithm Dedicated to Security Applications
Taha Beyrouthy
,
Laurent Fesquet
Development of a SoC for Digital Television Set-Top Box: Architecture and System Integration Issues
André Borin Soares
,
Alexsandro Cristóv?o Bonatto
,
Altamiro Amadeu Susin
Self-Adaptive On-Chip System Based on Cross-Layer Adaptation Approach
Kais Loukil
,
Nader Ben Amor
,
Mohamed Abid
,
Jean Philippe Diguet
Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA
Emna Amouri
,
Habib Mehrez
,
Zied Marrakchi
Performance Modeling for FPGAs: Extending the Roofline Model with High-Level Synthesis Tools
Bruno da Silva
,
An Braeken
,
Erik H. D’Hollander
,
Abdellah Touhafi
Runtime Scheduling, Allocation, and Execution of Real-Time Hardware Tasks onto Xilinx FPGAs Subject to Fault Occurrence
Xabier Iturbe
,
Khaled Benkrid
,
Chuan Hong
,
Ali Ebrahim
,
Tughrul Arslan
,
Imanol Martinez
Selected Papers from the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011)
René Cumplido
,
Peter Athanas
,
Jürgen Becker
Selected Papers from the Symposium on Integrated Circuits and Systems Design (SBCCI 2011)
Massimo Conti
,
Elmar Melcher
,
Jürgen Becker
,
Alisson Brito
,
Oliver Sander
Hardware Accelerators Targeting a Novel Group Based Packet Classification Algorithm
O. Ahmed
,
S. Areibi
,
G. Grewal
Design and Implementation of an Embedded NIOS II System for JPEG2000 Tier II Encoding
John M. McNichols
,
Eric J. Balster
,
William F. Turri
,
Kerry L. Hill
Rainbow: An Operating System for Software-Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs
Krzysztof Jozwik
,
Shinya Honda
,
Masato Edahiro
,
Hiroyuki Tomiyama
,
Hiroaki Takada
An Impulse-C Hardware Accelerator for Packet Classification Based on Fine/Coarse Grain Optimization
O. Ahmed
,
S. Areibi
,
R. Collier
,
G. Grewal
Frequency Optimization Objective during System Prototyping on Multi-FPGA Platform
Mariem Turki
,
Zied Marrakchi
,
Habib Mehrez
,
Mohamed Abid
Using Partial Reconfiguration and Message Passing to Enable FPGA-Based Generic Computing Platforms
Manuel Salda?a
,
Arun Patel
,
Hao Jun Liu
,
Paul Chow
An FPGA-Based Omnidirectional Vision Sensor for Motion Detection on Mobile Robots
Jones Y. Mori
,
Janier Arias-Garcia
,
Camilo Sánchez-Ferreira
,
Daniel M. Mu?oz
,
Carlos H. Llanos
,
J. M. S. T. Motta
Occam-pi for Programming of Massively Parallel Reconfigurable Architectures
Zain-ul-Abdin
,
Bertil Svensson
Redsharc: A Programming Model and On-Chip Network for Multi-Core Systems on a Programmable Chip
William V. Kritikos
,
Andrew G. Schmidt
,
Ron Sass
,
Erik K. Anderson
,
Matthew French
QoSS Hierarchical NoC-Based Architecture for MPSoC Dynamic Protection
Johanna Sepulveda
,
Ricardo Pires
,
Guy Gogniat
,
Wang Jiang Chau
,
Marius Strum
Performance Analysis Techniques for Multi-Soft-Core and Many-Soft-Core Systems
David Castells-Rufas
,
Eduard Fernandez-Alonso
,
Jordi Carrabina
Cellular Automata-Based Parallel Random Number Generators Using FPGAs
David H. K. Hoe
,
Jonathan M. Comer
,
Juan C. Cerda
,
Chris D. Martinez
,
Mukul V. Shirvaikar
Novel Dynamic Partial Reconfiguration Implementation of K-Means Clustering on FPGAs: Comparative Results with GPPs and GPUs
Hanaa M. Hussain
,
Khaled Benkrid
,
Ali Ebrahim
,
Ahmet T. Erdogan
,
Huseyin Seker
An Optimization-Based Reconfigurable Design for a 6-Bit 11-MHz Parallel Pipeline ADC with Double-Sampling S&H
Wilmar Carvajal
,
Wilhelmus Van Noije
Algorithm and Hardware Design of a Fast Intra Frame Mode Decision Module for H.264/AVC Encoders
Daniel Palomino
,
Guilherme Corrêa
,
Cláudio Diniz
,
Sergio Bampi
,
Luciano Agostini
,
Altamiro Susin
A Protein Sequence Analysis Hardware Accelerator Based on Divergences
Juan Fernando Eusse
,
Nahri Moreano
,
Alba Cristina Magalhaes Alves de Melo
,
Ricardo Pezzuol Jacobi
A Hardware Efficient Random Number Generator for Nonuniform Distributions with Arbitrary Precision
Christian de Schryver
,
Daniel Schmidt
,
Norbert Wehn
,
Elke Korn
,
Henning Marxen
,
Anton Kostiuk
,
Ralf Korn
The “Chimera”: An Off-The-Shelf CPU/GPGPU/FPGA Hybrid Computing Platform
Ra Inta
,
David J. Bowman
,
Susan M. Scott
Exploration of Uninitialized Configuration Memory Space for Intrinsic Identification of Xilinx Virtex-5 FPGA Devices
Oliver Sander
,
Benjamin Glas
,
Lars Braun
,
Klaus D. Müller-Glaser
,
Jürgen Becker
On the Feasibility and Limitations of Just-in-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors
Mariusz Grad
,
Christian Plessl
A Fault Injection Analysis of Linux Operating on an FPGA-Embedded Platform
Joshua S. Monson
,
Mike Wirthlin
,
Brad Hutchings
Redesigned-Scale-Free CORDIC Algorithm Based FPGA Implementation of Window Functions to Minimize Area and Latency
Supriya Aggarwal
,
Kavita Khare
A Memory Hierarchy Model Based on Data Reuse for Full-Search Motion Estimation on High-Definition Digital Videos
Alba Sandyra Bezerra Lopes
,
Ivan Saraiva Silva
,
Luciano Volcan Agostini
A Convolve-And-MErge Approach for Exact Computations on High-Performance Reconfigurable Computers
Esam El-Araby
,
Ivan Gonzalez
,
Sergio Lopez-Buedo
,
Tarek El-Ghazawi
An Evaluation of an Integrated On-Chip/Off-Chip Network for High-Performance Reconfigurable Computing
Andrew G. Schmidt
,
William V. Kritikos
,
Shanyuan Gao
,
Ron Sass
HoneyComb: An Application-Driven Online Adaptive Reconfigurable Hardware Architecture
Alexander Thomas
,
Michael Rückauer
,
Jürgen Becker
Placing Multimode Streaming Applications on Dynamically Partially Reconfigurable Architectures
S. Wildermann
,
J. Angermeier
,
E. Sibirko
,
J. Teich
Optimizing Investment Strategies with the Reconfigurable Hardware Platform RIVYERA
Christoph Starke
,
Vasco Grossmann
,
Lars Wienbrandt
,
Sven Koschnicke
,
John Carstens
,
Manfred Schimmler
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