One Way of Output Voltage Hold Circuit Improvement at Low Resistance Comparator

The article presents a way of improvement the important performances of an electronic low resistance comparator. The practical usage of a realized instrument prototype shows some disadvantages: the time until the result appears at the display is to long (the stationary state establishing sequence should be shorter) because of the negative influence of parasitic voltages. Modification of output voltage hold circuit gives quite convenient instrument response time. The parasitic voltage disturbance is decreased to acceptable value, even though the comparator is modified for multirange measurement. The paper describes some details of a solution and its conformation in practical usage.