A Low Power and Small Die-Size Phase Lock Loop Circuit Using Semi-Digital Storage

A conventional low-bandwidth Phase Lock Loop (PLL) requires an external capacitor and a big on-chip ripple capacitor. A new PLL architecture is proposed in this paper, which replaces the large external capacitor in the loop filter by semi-digital storage cells. PVT compensation is achieved using the information stored digitally in the storage cells. Since the total value of the on-chip capacitor is reduced drastically, the proposed PLL architecture has a small chip size and a very low power consumption. The design is validated by a silicon implementation. The proposed architecture can also be extended to the design of high bandwidth PLLs.