Design of DDR3 SDRAM controller

DDR3 SDRAM Memory controller is the interface between DDR3 memory and the user. The design consists of front end and back end modules. The memory controller manages the flow of data going to and from the main memory. The front end provides interface to the user side and it consists of read data, write data and attributes FIFO. It is followed by request breaker. The arbiter decides the order in which the requests should be executed. The back end provides interface to the memory side and consists of calibration logic, data path, application address FIFO, application read and write FIFO. Software used for designing the RTL Schematic, state diagrams and flow diagrams is DIA, can be done using Orcad as well. The code has been implemented in VHDL. GVIM editor has been used to write the code. The code has been tested on ModelSim simulator as per the industry norms.