Area-Efficient and High Speed ML MAP Processor Design Using DB/SB Decoding Technique

In communication systems, specifically wirelessmobile communication applications, Size and Speed aredominant factors while meeting the performance requirements.Turbo codes play an important role in such practical applicationsdue to their better error-correcting capability. In Turbodecoders, Maximum A Posterior probability (MAP) algorithmhas been widely used for its optimum error correctingperformance. But it is very difficult to design high-speed MAPDecoder because of its recursive computations. This paperproposes a Max-Log maximum a posteriori (ML-MAP)algorithm with dual mode SB/DB decoding. A Parallel VLSIarchitecture comprising multiple SISO elements, to form LogLikelihood ratio (LLR) unit in order to reduce the critical pathdelay. A dual mode single-binary (SB) and double-binary (DB)decoding algorithm has been used to reduce the arbitrary blocksizes for high throughput decoding. The computational modulesand storages of the dual-mode (SB/DB) MAP decoding aredesigned to achieve high area utilization. This architecture with aSB/DB decoding can achieve comparable processing speed about11 % and area efficiency of 5.71 bits/mm2.