A Fast Serial Multiplier Design using Ripple Counters

Multipliers are the fundamental components of many digital systems. Low power and high speed multiplier circuits are highly demanded. It is not possible to achieve both the criteria simultaneously.Therefore, there exists some trade-off between speed and power consumption in the design of a binary multiplier.The partial product (PP) formation and reduction of the partial product tree height in serial multipliers is our primary concern. In existing CSAS architecture of partial product formation is carried out in 2n clock cycles, where n is the number of operand bits. Here, the critical path is along the full adders and AND gates. The disadvantage of this method is increased delay as it involves 2n computational clock cycles. This disadvantage is overcome by using the concept of data accumulation by ripple counters. Column compression technique is used for the reduction of partial product tree height. Unlike the CSAS architecture, the critical path in this technique is found only along the AND gates. The partial product formation is done in n clock cycles instead of 2n clock cycles and hence delay is reduced. Moreover, the counters change states only when input is ‘1’, which leads to low switching power.The final product is computed by the Ripple carry adder (RCA) in both the above architectures. RCA is replaced by KSA for improved performance. The average connection delay in the multiplier architecture due to KSA is reduced and is expressed in terms of nano seconds.