Extremely Low Power FIR Filter for a Smart Dust Sensor Module

Digital filters are common components in many applications today, also in for sensor systems,such as large-scale distributed smart dust sensors. For these applications the power consumptionis very critical, it has to be extremely low. With the transistor technology scaling becoming moreand more sensitive to e.g. gate leakage, it has become a necessity to find ways to minimize theflow of leakage in current CMOS logic. This paper studies sub-threshold source coupled logic(STSCL) in a 45-nm process. The STSCL can be used instead of traditional CMOS to meet thelow power and energy consumption requirements. The STSCL style is in this paper used todesign a digital filter, applicable for the audio interface of a smart dust sensor where the samplefrequency will be 44.1 kHz. A finite-length impulse response (FIR) filter is used with transposeddirect form structure and for the coefficient multiplication five-bit canonic signed digit [7] basedserial/parallel multipliers were used. The power consumption is calculated along with the delay inorder to present the power delay product (PDP) such that the performance of the sub-thresholdlogic can be compared with corresponding CMOS implementation. The simulated results shows asignificant reduction in energy consumption (in terms of PDP) with the system running at a supplyvoltage as low as 0.2 V using STSCL.