Design and Simulation of a Modified Architecture of Carry Save Adder

This paper presents a technology-independent design and simulation of a modified architecture ofthe Carry-Save Adder. This architecture is shown to produce the result of the addition fast and byrequiring a minimum number of logic gates. Binary addition is carried out by a series of XOR,AND and Shift-left operations. These operations are terminated with a completion signalindicating that the result of the addition is obtained. Because the number of shift operationscarried out varies from 0 to n for n-bit addends, a behavioral model was developed in which allthe possible addends having 2- to 15-bits were applied. A mathematical model was deductedfrom the data and used to predict the average number of shift required for standard binarynumbers such as 32, 64 or 128-bits. 4-bit prototypes of this adder were designed and simulatedin both synchronous and asynchronous modes of operation.