High secured and area optimized Online Memory Testing for efficient Fault Diagnostic Systems

The main intention of this project is to recommend a fault diagnoses structure for revealing of any software or hardware or permanent failures in the embedded read only memories. BIST controller, along with row selector and column selector is designed to meet necessities of at speed test thus enabling detection of timing defects. The projectedapproach offers a simple test flow and does not require intensive communications between a BIST controller and a tester. The system rests on partitioning of rows and columns of the memory array by employing low cost test logic. It is intendedto meet requirements of at-speed test thus enabling detection of timing defects.