Design of Energy Efficient Arithmetic Circuits Using Charge Recovery Adiabatic Logic

Low power has emerged as a principle theme in today electronic industry. Energy efficiency is one of the most important features of modern electronic systems designed for high speed and portable applications. The power consumption of the electronic devices can be reduced by adopting different design styles. Adiabatic logic style is said to be an attractive solution for such low power electronic applications. This paper presents an energy efficient technique for digital circuits that uses adiabatic logic. The proposed technique has less power dissipation when compared to the conventional CMOS design style. This paper evaluates the full adder in different adiabatic logic styles and their results were compared with the conventional CMOS design. The simulation results indicate that the proposed technique is advantageous in many of the low power digital applications.