Design of Memory Based Implementation Using LUT Multiplier

Multiplication is major arithmetic operation in signal processing. In ALU’s the multiplier uses lookup-table (LUT) as memory for their computations. We do not find any significant work on LUT optimization for memory-based multiplication. In this project, the anti symmetric product coding (APC) and odd-multiple storage (OMS) are used for lookup-table (LUT) design for memory-based multipliers used in the signal processing applications like filter design. Each of this technique results in the reduction of LUT size by a factor of two. A different form of APC and modified OMS scheme can be combined for efficient memory implementation which reduces LUT size to one-fourth of the conventional LUT. The proposed design of LUTbased multiplier involves less area-delay product for higher word sizes due to operand decomposition than the canonical-signed-digit (CSD)-based multipliers. The coding is proposed to be done in Veriolg HDL and synthesized using XillinxISE10.1i and implemented using Spartan3E FPGA