Design of Reversible Fault Tolerant Programmable Logic Arrays with Vector Orientation

In recent years, reversible logic has emerged as a promising computing paradigm having application in low power CMOS, quantum computing and error detecting. Reversible computing dissipates zero energy in terms of information loss and also it can detect error of circuit by keeping unique input-output mapping. In this paper, we have proposed a regular structure of Reversible Fault Tolerant Programmable Logic Arrays (RFTPLAs) and corresponding algorithms for construction of RFTPLAs. Proposed algorithms can realize ESOP (Exclusive Sum-of-Products) operations in terms of multi-output functions by using minimum numbers of gates, garbage bits and quantum costs. In our design the novel properties of FRG (Fredkin Gate) and F2G (Feynman Double Gate) gates are used for the realization of proposed designs. Finally, we compare the proposed design with existing RPLA.