Arbiter Design Using Verilog for Switching to Communicate in Between Multiple Resources

This project attempts to describe a special type of circuit called an arbiter to be used in a larger design called switch to communicate in between multiple resources. The design specification gives results according to suggested implementation for the circuit. Finally, possibilities for addition, revision and testing structure for an integrated circuit implementation of the arbiter will be proposed. The main contribution of this paper is the design and optimization of asynchronous arbiter circuit using CMOS, Bi-cmos and synchronous fast round- robin arbiters and the design of On-Chip Scheduler. Scheduler is expressed here in verilog RTL and simulation results are presented to indicate the performance. This paper will present design ideas for effectively interfacing to an arbiter and investigate coding styles for some common arbitration schemes. When Circuits need to be constructed out of several self-timed parts, the arbitration is often required for the asynchronous design. We consider the creation of the general purpose arbiter delegating M resources to N clients. Firstly, the task is done for the case of one to three resources being offered to one to three clients and preserving capability to allow one to all clients accessing resources simultaneously using verilog.