Realization of Multistage FIR Filters using Pipelining-Interleaving

Multistage digital filters can be one of the solutions for the realization of filters with a narrow transition zone. If requirements for the width of transition zone are too strict, then they are the only alternative, and the decimation/interpolation must be performed in several steps. Combining decimation/interpolation operations related to the implementation of multi-channel filters in the PI (pipelining/interleaving) technique can give an efficient structure of multichannel multistage filter. Using the advantages offered by newer generations of FPGA chips in terms of digital design structure, it is possible to realize such filters with considerable savings of hardware resources and reduce the effect of finite length codeword. This paper proposes such an efficient implementation and presents the results of such a realization with FPGA components.