Modelling and analysis of the effect of stacking chips with TSVs in 3D IC package encapsulation process

This paper presents the modelling and analysis of the encapsulation processfor three-dimensional (3D) stacking-chip package with through-silicon via (TSV)integration. The fluid-structure interaction of the 3D stacking-chip package encapsulationwas modelled by finite volume and finite element codes, which were solved separately.The effect of the increase in the number of stacking chips was analysed. The visualisationof the 3D stacking-chip package encapsulation process was presented at different fillingtimes. The void formation around the stacking chips was identified for each case. Thedisplacement and von Mises stress for the copper through-silicon vias were determined.The use of designed inlet-outlet heights in the integrated circuit package maintained thefilling time of the encapsulation process and reduced the void of the packages as thenumber of stacking chips increased. The encapsulation model facilitated a clearvisualisation and enhanced fundamental understanding of the design of a 3D integratedcircuit encapsulation. The proposed analysis is expected to be a reference and guide inthe design and improvement of 3D integration packages.