Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer

Placement is important in VLSI physical design as it determines the time-to-market and chip's reliability. In this paper, a new floorplan representation which couples with Ant System, namely Corner Insertion Sequence (CIS) is proposed. Though CIS's search complexity is smaller than the state-of-the-art representation Corner Sequence (CS), CIS adopts a preset boundary on the placement and hence, leading to search bound similar to CS. This enables the previous unutilized corner edges to become viable. Also, the redundancy of CS representation is eliminated in CIS leads to a lower search complexity of CIS. Experimental results on Microelectronics Center of North Carolina (MCNC) hard block benchmark circuits show that the proposed algorithm performs comparably in terms of area yet at least two times faster than CS.