Considering the variety of studies that have been reported in low-power designing era, the subthreshold design trend in Very Large Scale Integrated (VLSI) circuits has experienced a significant development in recent years. Growing need for the lowest power consumption has been the primary motivation for increase in research in this area although other goals, such as lowest energy delay production, have also been achieved through sub-threshold design. There are, however, few extensive studies that provide a comprehensive design insight to catch up with the rapid pace and large-scale implementations of sub-threshold digital design methodology. This paper presents a complete review of recent studies in this field and explores all aspects of sub-threshold design methodology. Moreover, near-threshold design and low-power pipelining are also considered to provide a general review of sub-threshold applications. At the end, a discussion about future directions in ultralow-power design is also included. 1. Introduction Subthreshold digital circuits are now well known to ultralow-power designers and have frequently and successfully been used for applications such as implanted sensors and mobile peripheral processors. However, performance degradation and high sensitivity to Process/Voltage/Temperature (PVT) variations are the primary challenges that have confined subthreshold circuit implementations to low-activity applications. There are many recent review papers covering the subjects of sub/near-threshold digital design and their challenges. The goal of this review, however, is to cover a boarder range of designs, to show the interrelation of different solutions for low-power digital design and review the recent updates and new advances in ultralow-power era. Some of useful and comprehensive reviews are as follows. Authors in [1] presented a detailed review that discussed the advantages/disadvantages of subthreshold design, and mathematical equations required for the subthreshold circuits. The paper also covered variation problems briefly and presented subthreshold design techniques for Static Random Access Memories (SRAM) design followed by design techniques for multiprocessing. These discussions make [1] one of the most inclusive early papers. In [2] authors have focused on variations and leakage reduction, to a greater extent, and besides DC-DC converters have also been discussed. In one of the recent reviews, authors (see [3]) presented a detailed review of subthreshold design by exploring subthreshold modelling methods, a few leakage reduction techniques, a
References
[1]
S. Hanson, B. Zhai, K. Bernstein et al., “Ultralow-voltage minimum-energy CMOS,” IBM Journal of Research and Development, vol. 50, no. 4-5, pp. 469–490, 2006.
[2]
J. Kwong and A. P. Chandrakasan, “Advances in ultra-low-voltage design,” IEEE Solid-State Circuits Newsletter, vol. 13, pp. 20–27, 2008.
[3]
S. K. Gupta, A. Raychowdhury, and K. Roy, “Digital computation in subthreshold region for ultralow-power operation: a device-circuit-architecture codesign perspective,” Proceedings of the IEEE, vol. 98, no. 2, pp. 160–190, 2010.
[4]
S. Hanson, M. Seok, Y. S. Lin et al., “A low-voltage processor for sensing applications with picowatt standby mode,” IEEE Journal of Solid-State Circuits, vol. 44, no. 4, pp. 1145–1155, 2009.
[5]
J. Kwong and A. P. Chandrakasan, “Variation-driven device sizing for minimum energy sub-threshold circuits,” in Proceedings of the 2006 International Symposium on Low Power Electronics and Design (ISLPED '06), pp. 8–13, New York, NY, USA, October 2006.
[6]
D. Bol, R. Ambroise, D. Flandre, and J. D. Legat, “Interests and limitations of technology scaling for subthreshold logic,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 10, pp. 1508–1519, 2009.
[7]
F. Moradi, D. T. Wisland, H. Mahmoodi, A. Peiravi, S. Aunet, and T. V. Cao, “New subthreshold concepts in 65？nm CMOS technology,” in Proceedings of the 10th International Symposium on Quality Electronic Design (ISQED '09), pp. 162–166, San Diego, Calif, USA, March 2009.
[8]
D. Bol, D. Flandre, and J. D. Legat, “Technology flavor selection and adaptive techniques for timing-constrained 45？nm subthreshold circuits,” in Proceedings of the 14th ACM/IEEE International Symposium on Low Power Electronics and Design, pp. 21–26, New York, NY, USA, August 2009.
[9]
K. Roy, J. P. Kulkarni, and M. E. Hwang, “Process-tolerant ultralow voltage digital subthreshold design,” in Proceedings of IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF '08), pp. 42–45, Orlando, Fla, USA, January 2008.
[10]
Y. Pu, J. P. De Gyvez, H. Corporaal, and Y. Ha, “An ultra-low-energy multi-standard JPEG Co-processor in 65？nm CMOS with sub/near threshold upply voltage,” IEEE Journal of Solid-State Circuits, vol. 45, no. 3, pp. 668–680, 2010.
[11]
B. Zhai, S. Pant, L. Nazhandali et al., “Energy-efficient subthreshold processor design,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 8, pp. 1127–1137, 2009.
[12]
S. Hanson, B. Zhai, M. Seok et al., “Exploring variability and performance in a sub-200-mV processor,” IEEE Journal of Solid-State Circuits, vol. 43, no. 4, pp. 881–890, 2008.
[13]
M. E. Hwang and K. Roy, “ABRM: adaptive β-ratio modulation for process-tolerant ultradynamic voltage scaling,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 2, pp. 281–290, 2010.
[14]
S. Hanson, B. Zhai, M. Seok et al., “Performance and variability optimization strategies in a sub-200？mV, 3.5？pJ/inst, 11？nW subthreshold processor,” in Proceedings of IEEE Symposium on VLSI Circuits, pp. 152–153, Kyoto, Japan, June 2007.
[15]
I. J. Chang, J. J. Kim, S. P. Park, and K. Roy, “A 32？kb 10T sub-threshold sram array with bit-interleaving and differential read scheme in 90？nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 44, no. 2, pp. 650–658, 2009.
[16]
M. E. Sinangil, N. Verma, and A. P. Chandrakasan, “A reconfigurable 8T ultra-dynamic voltage scalable (U-DVS) SRAM in 65？nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 44, no. 11, pp. 3163–3173, 2009.
[17]
N. Verma and A. P. Chandrakasan, “A 256？kb 65？nm 8T subthreshold SRAM employing sense-amplifier redundancy,” IEEE Journal of Solid-State Circuits, vol. 43, pp. 141–149, 2008.
[18]
B. Zhai, S. Hanson, D. Blaauw, and D. Sylvester, “A variation-tolerant sub-200？mV 6-T subthreshold SRAM,” IEEE Journal of Solid-State Circuits, vol. 43, no. 10, pp. 2338–2348, 2008.
[19]
M. Sharifkhani and M. Sachdev, “An energy efficient 40？Kb SRAM module with extended read/write noise margin in 0.13？μm CMOS,” IEEE Journal of Solid-State Circuits, vol. 44, no. 2, pp. 620–630, 2009.
[20]
B. Zhai, D. Blaauw, D. Sylvester, and S. Hanson, “A sub-200？mV 6T SRAM in 0.13？μm CMOS,” in Proceedings of the 54th IEEE International Solid-State Circuits Conference (ISSCC '07), pp. 332–606, San Francisco, Calif, USA, February 2007.
[21]
J. P. Kulkarni, K. Kim, and K. Roy, “A 160？mV, fully differential, robust schmitt trigger based sub-threshold SRAM,” in Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED '07), pp. 171–176, New York, NY, USA, August 2007.
[22]
B. Zhai, R. G. Dreslinski, D. Blaauw, T. Mudge, and D. Sylvester, “Energy efficient near-threshold chip multi-processing,” in Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED '07), pp. 32–37, Portland, Ore, USA, August 2007.
[23]
Y. He, Y. Pu, Z. Ye et al., “Xetal-pro: an ultra-low energy and high throughput SIMD processor,” in Proceedings of the 47th Design Automation Conference (DAC '10), pp. 543–548, Anaheim, Calif, USA, June 2010.
[24]
S. Seo, R. G. Dreslinski, M. Who, C. Chakrabarti, S. Mahlke, and T. Mudge, “Diet SODA: a power-efficient processor for digital cameras,” in Proceedings of the 16th ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED '10), pp. 79–84, Redondo Beach, Calif, USA, August 2010.
[25]
R. G. Dreslinski, M. Wieckowski, D. Blaauw, D. Sylvester, and T. Mudge, “Near-threshold computing: reclaiming moore's law through energy efficient integrated circuits,” Proceedings of the IEEE, vol. 98, no. 2, pp. 253–266, 2010.
[26]
M. R. Kakoee, A. Sathanur, A. Pullini, J. Huisken, and L. Benini, “Automatic synthesis of near-threshold circuits with fine-grained performance tunability,” in Proceedings of the 16th ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED '10), pp. 401–406, Austin, Tex, USA, August 2010.
[27]
S. E. Lee, C. Wilkerson, M. Zhang, R. Yavatkar, S. L. Lu, and N. Bagherzadeh, “Low power adaptive pipeline based on instruction isolation,” in Proceedings of the 10th International Symposium on Quality Electronic Design (ISQED '09), pp. 788–793, March 2009.
[28]
S. Ghosh, J. H. Choi, P. Ndai, and K. Roy, “O2C: occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessors,” in Proceedings of the 13th ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED '08), pp. 189–192, Bangalore, India, August 2008.
[29]
N. Toosizadeh, S. G. Zaky, and J. Zhu, “Varipipe: low-overhead variable-clock synchronous pipelines,” in Proceedings of IEEE International Conference on Computer Design, ICCD 2009, pp. 117–124, October 2009.
[30]
M. Ghasemazar, B. Amelifard, and M. Pedram, “A mathematical solution to power optimal pipeline design by utilizing soft edge flip-flops,” in Proceedings of the 13th ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED '08), pp. 33–38, Bangalore, India, August 2008.
[31]
X. Liang, G. Y. Wei, and D. Brooks, “ReVIVaL: a variation-tolerant architecture using voltage interpolation and variable latency,” in Proceedings of the 35th International Symposium on Computer Architecture (ISCA '08), pp. 191–202, June 2008.
[32]
B. Zhai, L. Nazhandali, J. Olson et al., “A 2.60？pJ/inst subthreshold sensor processor for optimal energy efficiency,” in Proceedings of the IEEE Symposium on VLSI Circuits, Digest of Technical Papers (VLSIC '06), pp. 154–155, June 2006.
[33]
M. G. Jeong, T. Nakura, M. Ikeda, and K. Asada, “Moebius circuit: dual-rail dynamic logic for logic gate level pipeline with error gate search feature,” in Proceedings of the 19th ACM Great Lakes Symposium on VLSI (GLSVLSI '09), pp. 177–180, Boston, Mass, USA, May 2009.
[34]
O. Azizi, A. Mahesri, B. C. Lee, S. J. Patel, and M. Horowitz, “Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis,” in Proceedings of the 37th International Symposium on Computer Architecture (ISCA '10), pp. 26–36, Saint-Malo, France, June 2010.
[35]
K. Hirose, Y. Manzawa, M. Goshima, and S. Sakai, “Delay-compensation flip-flop with in-situ error monitoring for low-power and timing-error-tolerant circuit design,” Japanese Journal of Applied Physics, vol. 47, no. 4, pp. 2779–2787, 2008.
[36]
D. Ernst, K. Nam Sung, S. Das et al., “Razor: a low-power pipeline based on circuit-level timing speculation,” in Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-36, pp. 7–18, 2003.
[37]
M. J. Turnquist and L. Koskinen, “Sub-threshold operation of a timing error detection latch,” in Proceedings of the Research in Microelectronics and Electronics, 2009. PRIME 2009. Ph.D., pp. 124–127, July 2009.
[38]
D. Blaauw, S. Kalaiselvan, K. Lai et al., “Razor II: in situ error detection and correction for PVT and SER tolerance,” in Proceedings of the IEEE International Solid State Circuits Conference (ISSCC '08), pp. 399–622, February 2008.
[39]
S. Das, S. Pant, D. Roberts et al., “A self-tuning DVS processor using delay-error detection and correction,” in Proceedings of the Symposium on VLSI Circuits, 2005, Digest of Technical Papers, pp. 258–261, June 2005.
[40]
K. A. Bowman, J. W. Tschanz, N. S. Kim et al., “Energy-efficient and metastability-immune timing-error detection and instruction-replay-based recovery circuits for dynamic-variation tolerance,” in Proceedings of the IEEE International Solid State Circuits Conference (ISSCC '08). Digest of Technical Papers, pp. 402–623, February 2008.
