HIGH SPEED ROUTERS RELY ON WELL DESIGNED PACKET BUFFERS

All packet switches contain packet buffers to hold packets during times of congestion. High-speed routers rely on well-designed packet buffers that support multiple queues, provide large capacity and short response times and suggested combined SRAM/DRAM hierarchical buffer architectures to meet these challenges. This is particularly true for a shared memory switch where the memory needs to operate at times the line rate, where is the number of ports in the system. Even input queued switches must be able to buffer packets at the rate at which they arrive. We address these issues by first designing an efficient compact buffer that reduces the SRAM size requirement by (k – 1)/k. Then, we introduce a feasible way of coordinating multiple subsystems with a load-balancing algorithm that maximizes the overall system performance. Both theoretical analysis and experimental results demonstrate that our load-balancing algorithm and the distributed packet buffer architecture can easily scale to meet the buffering needs of high bandwidth links and satisfy the requirements of scale and support for multiple queues.