Reduced Comparator Flash ADC for ECG Applications

A CMOS based 4-bit Flash Analog to Digital Converter (ADC) design with reduced number of comparators than the conventional Flash Analog to Digital Converter and multiplexer based architecture is proposed. For improving the conversion rate, both the analog and digital parts of the ADC are fully modified and the architecture uses only 4 comparators instead of 15 as used in conventional flash ADC, thus saving considerable amount of power. The proposed 4-bit ADC is designed and simulated in TANNER tools with 1.2 V supply voltage using TSpice simulation