Reduced Computation Time In Fixed Width Booth Multiplier Using Baugh Wooley Method

Multiplier plays an important role in digital signal processing systems but it consumes much power and area, In order to reduce the power and area occupied by the multiplier. We opt for fixed width multiplier. Our proposed method is to design fixed-width multiplier using Baugh-Wooley (BW) algorithm. It simplifies a structure of multiplier with the aim of reducing power and increasing performance of system. In this method two topologies are in particularly selected as the most effective ones. The first one is based on a uniform coefficient quantization, while the second topology uses a non uniform quantization scheme. The novel fixed-width multiplier using Baugh-Wooley algorithm exhibit better accuracy with respect to previous solutions the novel ?xed-width multiplier topologies exhibit better accuracy with respect to previous solutions, close to the theoretical lower bound. The electrical performances of the proposed ?xed-width multi-pliers are compared with previous architectures. It is found that in most of the investigated cases the new topologies are Pareto-optimal regarding the area-accuracy trade-off.