Hardware Implementation of the Huffman Encoder for Data Compression Using Altera DE2 Board

This work will aim to describe hardware implementations of static and dynamic Huffman encoders written in VHDL.The flexibility of the design allows for hardware-based implementations using FPGAs. The proposed method will have the following properties: (1) high compression for test responses is expected because Huffman coding is well-known as a minimum block coding, (2) zero-aliasing compression can be achieved.(3) It would also reduce transmission time, storage space, translation table space and encoding times