FPGA IMPLEMENTATION OF AREA EFFICIENT ADAPTIVE FILTER USING ARRAY OF SENSORS

In this paper an area efficient Cordic based adaptive algorithm has been designed and simulated for Digital Signal Processing. An adaptive filter is useful whenever the statistics of the input signals to the filter are not known. Many adaptive algorithms like LMS, NLMS and RLS are used for adaptive filtering. An efficient QR decomposition based RLS algorithm is an efficient way to filter out noise signal but its area consumption is high. So for improving area a Cordic based approach is used.Cordic algorithm is very much hardware efficient, it omits the dependence on multipliers because it implement various operations with the help of shift-add operation. Instead of taking signal from one sensor, here array of sensor (microphones) is used, whichs play an important role in noise reduction and speech enhancement. The proposed Cordic QR decomposition based adaptive algorithm is designed using MATLAB and Xilinx ACCELDSP ,synthesized with Xilinx Synthesis Tool (XST), and implemented on SPARTAN-3an(xc3s700an-5fgg484) FPGA device. The proposed algorithm has been compared with conventional QRD based recursive least square in terms of area. The results show that the performance is almost similar, but area consumption is low. The proposed design can operate at an estimated frequency of 93.7 MHz along with the minimum period of 10.6710 ns the Spartan 3an device.