FPGA Based A New Low Power and Self-Timed AES 128-bit Encryption Algorithm for Encryption Audio Signal

This paper presents, a low power 128-bit Advanced Encryption Standard (AES) algorithm based on a novel asynchronous self-timed architecture for encryption of audio signals. An asynchronous system is defined as one where the transfers of information between combinatorial blocks without a global clock signal. The self-timed architectures are asynchronous circuits which perform their function based on local synchronization signals called hand shake, independently from the other modules. This new architecture reduced spikes on current consumption and only parts with valid data are working, and also this design does not need any clock pulse. A combinational logic based Rijndael S-Box implementation for the Substitution Byte transformation in AES is proposed, its low area occupancy and high throughput therefore proposed digital design leads to reduction in power consumption. Mix-columns transformation is implemented only based on multiply-by-2 and multiply-by-3 modules with combinational logic. The proposed novel asynchronous self-timed AES algorithm is modeled and verified using FPGA and simulation results from encryption of sound signals is presented, until original characteristics are preserved anymore and have been successfully synthesized and implemented using Xilinx ISE V7.1 and Virtex IV FPGA to target device Xc4vf100. The achieved power consumption is 283 mW in clock frequency of 100 MHz.