Implementing the ARM7 Soft Core Processor in FPGA

Today Soft processor cores are gaining importance for FPGA based embedded applications, where the end user can configure the processor as per his requirement and achieve the benefits of SOC by implementing other required logic on FPGA fabric. SOC systems require an FPGA with a processor core. Processor cores are classified as either “hard” or “soft.” Hard processor cores added to an FPGA are a hybrid approach, offering performance tradeoffs that fall somewhere between a traditional ASIC and an FPGA; they are available from several manufacturers with a number of different processor flavors. Soft cores, such as Altera’s Nios II and Xilinx’s MicroBlaze and PicoBlaze processors, use existing programmable logic elements from the FPGA to implement the processor logic. It is of great concern to build ARM soft processor cores in the context of FPGA based multiprocessor based SOC applications. ARM architecture is considered to be market dominant in the field of mobile phones and several other embedded applications. The ARM processor has been specifically designed to be small to reduce power consumption and extend battery operation. In this paper a subset of ARM 7, V4 instruction set will be implemented to cater for such applications. A selected set of 32 bit instructions will be implemented with single cycle data path and random logic based instruction decoder. The core shall be implemented with UART and SPI communication capabilities. The major blocks would be register file, barrel shifter, ALU, multiplier, program counter updating logic and controller. The ROM will be implemented to store the hex codes of a program which will be used to test the implemented ARM soft processor core. GNU ARM assembler generated hex codes will be used to validate the design. Result analysis done in Modelsim XE for simulation and in Xilinx XST for synthesis and in Chip scope for chip verification. This ARM processor embedded into FPGA which can be used for different applications like DSP and Image processing.