A Novel Low Power pattern Generation Technique for Concurrent Bist Architecture

This paper proposes a low power Linear Feedback Shift Register (LFSR) for Test Pattern Generation (TPG) technique with reducing power dissipation during testing. The correlations between the consecutive patterns are higher during normal mode than during testing. The proposed approach uses the concept of reducing the transitions in the test pattern generated by conventional LFSR. The goal of having intermediate patterns is to reduce the transitional activities of primary inputs which eventually reduce the switching activities inside the circuit under test, and hence, power consumption .The testing power is reduced by 46%with respect to the power consumed during the testing carried by conventional LFSR. Built-In Self-Test (BIST) techniques constitute an attractive and practical solution to the problem of testing VLSI circuits and systems. Input vector monitoring concurrent BIST schemes can circumvent problems appearing separately in on-line and in of-line BIST techniques