Power-Area trade-off for Different CMOS Design Technologies

With the advancement of technology, Integrated Chip (IC) has achieved smaller chip size with more functions integrated. Through the usage of more transistors, it has lead to an increase of power dissipation and undesired noise. As the design gets more complex, this results in slower speed. Hence, the demand for low power, fast speed is desired. In this paper an adder and logic circuits are designed in three different CMOS technology structures like complementary logic, ratio logic and dynamic logic. They all have a similar function, but the way of producing the intermediate nodes and the transistor count is different. The main objective of this paper is comparison of static CMOS adder, ratio logic adder and clocked cascade voltage switch logic adder (also known as dual rail domino) in terms of power dissipation and area. The designs are implemented on 45nm process models in tanner tools v13.0 s-Edit composer and simulations are carried out in T-Spice.