Implementation of Module Based Partial Reconfigurable Multiplier

A reconfigurable structure allows us to provide a large number of resources that can be used in different ways by different applications. This paper presents the design methodology of reconfigurable array multipliers. An 8-bit reconfigurable multiplier can execute one 8-bit and two 4-bit multiplications depending upon three control signals. The hardware overhead includes 192 two-input AND gates and 3 control signals. Comparing with the original 8-bit array multiplier which requires 4032 Full Adders and 4096 two-input AND gates, the hardware overhead is very small. With additional metal lines for interconnections, the hardware overhead will not increase the chip area. In other words, the high re-configurability of the developed circuit is achieved with negligible hardware overhead and virtually no performance overhead. The reconfigurable structure continues to use the conventional array multiplier with minor changes.Index Terms : Reconfiguration, Multiplier, FPGA