Parity Based Fault Detection Approach for the Low Power S-Box and Inverse S-Box

Advanced Encryption Standard (AES) has been made as the first choice for many critical applications because of the high level of security and the fast hardware and software implementations, many of which are power and resource constrained and requires reliable and efficient hardware implementations. In addition to the efficiency requirements of the AES, it must be reliable against transient and permanent internal faults or malicious faults aiming at revealing the secret key. In this paper, parity-based fault detection architecture of the S-box and the Inverse S-box for designing high performance fault detection structures of the AES is presented. The proposed parity-based fault detection approach is based on the low-cost composite field implementations of the S-box and the inverse S-box. Instead of using look-up tables for the S-box (Inverse S-box) and its parity prediction, logical gate implementations based on the composite field are utilized and hence the area gets reduced. This parity-based fault detection scheme reaches the maximum fault coverage when compared to other methods of fault detection. The proposed fault detection of the S-box and the inverse S-box in this paper have the least area and power consumption compared to their counterparts with similar fault detection capabilities