REALIZATION OF IP CORE FOR ROBOT CONTROLLED TRENCHING SYSTEM

An IP Core of a Robot based Trenching System has been designed modeled on Intel's 8051 Microcontroller. The designed IP Core realizes all 256 instructions of 8051 and also the resources available on a generic 8051 chip. The designed system has both internal and external ROM and RAM, an address generator, and a decoder. Realization includes the timer functions, serial communication and interrupts. A comprehensive test bench has been developed and all instructions and the resources on chip have been fully tested. The code is RTL compliant and is Technology and Platform Independent. It features a high degree of parallelism and heavy pipelining targeted on FPGA or ASIC. The designed system is more efficient in terms of processing speed by over 7 to 50 times when compared to the original Intela€ s 8051. With this design, 8051 microcontroller would be given a new lease of life even when it becomes obsolete with time. The agricultural implement IP Core design has been primarily targeted on the Xilinx, Spartan 3 FPGA and works at a conservative operating frequency of 50 MHz.