A New Leakage Power Reduction Technique for CMOS VLSI Circuits

A robust method which is equally effectual for static power control in CMOS VLSI circuits for System on Chip (Soc) applications in deep submicron technologies is proposed. Referring to the International Technology Roadmap for Semiconductors (ITRS), the total power dissipation may be significantly contributed by leakage power dissipation. To reduce leakage the proposed method introduces two self controlled stacked leakage control transistors (LT) between Vdd and ground, which offers high resistance, when it is in off state. The gate and substrate of each LT’s are tied together to introduce Dynamic Threshold voltage MOSFET (DTMOS). This proposed method is intuitively momentous and leads to better performance measure in terms of dynamic power, leakage power propagation delay and Power Delay Product (PDP) with standard threshold devices. The experiment and simulation results show that the proposed method effectively outperforms than the base case with little area overhead.