Design of Low Power and Area Efficient Architecture for Reconfigurable FIR Filter

Finite Impulse Response (FIR) filters are widely applied in multi-standard wireless communications. These filters provide linear phase and absolute stability. The FIR offers a low sensitivity for the coefficient quantization errors. These properties increase the usage of FIR filter. In this paper, reconfigurable digital filter architecture is proposed. The approach is well suited if the filter order is fixed. The filter is dynamically reconfigured by changing the filter order. The order is changed by turning of the multiplier whose inputs are mitigate to be eliminated. The complexity of linear phase FIR filters is dominated by the number of adders (sub-tractors) in the coefficient multiplier. The Common Sub-expression Elimination (CSE) algorithm reduces number of adders in the multipliers and dynamically reconfigurable filters can be efficiently implemented. The proposed filter architectures offers power and area reduction over the existing FIR filter implementation.