Design of RS (255, 251) Encoder and Decoder in FPGA

Detection and correction of errors in digital data is an important issue for the modern communication systems. Therefore an efficient error control code is needed to protect the digital data. In high speed communication system Reed-Solomon codes are widely used to provide error protection especially against the burst errors. Reed-Solomon codes are cyclic, non-binary codes. In this paper RS(255, 251)encoder and decoder have been designed and implemented on an FPGA platform.