Design of Reversible Multipliers for Linear Filtering Applications in DSP

Multipliers in DSP computations are crucial. Thus modern DSP systems need to develop low powermultipliers to reduce the power dissipation. One of the efficient ways to reduce power dissipation is by theuse of bypassing technique. If a bit in the multiplier and/or multiplicand is zero the whole array of rowand/or diagonal will be bypassed and hence the name bypass multipliers. This paper presents the columnBypass multiplier and 2-D bypass multiplier using reversible logic; Reversible logic is a more prominenttechnology, having its applications in Low Power CMOS and quantum computations. The switchingactivity of any component in the bypass multiplier depends only on the input bit coefficients. Thesemultipliers find application in linear filtering FFT computational units, particularly during zero paddingwhere there will be umpteen numbers of zeros. A bypass multiplier reduces the number of switchingactivities as well as the power consumption, above which reversible logic design acts to further almostnullify the dissipations