Realization of Transmitter and Receiver Architecture for Downlink Channels in 3-GPP LTE

Long Term Evolution (LTE), the next generation of radio technologies designed to increase the capacityand speed of mobile networks. The future communication systems require much higher peak rate for the airinterface but very short processing delay. This paper mainly focuses on to improve the processing speedand capability and decrease the processing delay ofthe downlink channels using the parallel processingtechnique. This paper proposes Parallel ProcessingArchitecture for both transmitter and receiver forDownlink channels in 3GPP-LTE. The Processing stepsinclude Scrambling, Modulation, Layer mapping,Precoding and Mapping to the REs in transmitter side. Similarly demapping from the REs, Decoding andDetection, Delayer mapping and Descrambling in Receiver side. Simulation is performed by usingmodelsim and Implementation is achieved using PlanAhead tool and virtex 5 FPGA.Implemented resultsare discussed in terms of RTL design, FPGA editor,power estimation and resource estimation.